Hosted at
35th International Conference
on Massive Storage Systems
and Technology (MSST 2019)
May 20 — 24, 2019

Sponsored by Santa Clara University,
School of Engineering


Since the conference was founded, in 1974, by the leading national laboratories, MSST has been a venue for massive-scale storage system designers and implementers, storage architects, researchers, and vendors to share best practices and discuss building and securing the world's largest storage systems for high-performance computing, web-scale systems, and enterprises.
    



Hosted at
Santa Clara University
Santa Clara, CA

Tutorial and Invited Track Speaker

Bill Gervasi, Nantero, Inc.


Bill Gervasi
Mr. Gervasi has over 40 years of experience in high speed memory subsystem definition, design, and product development. Career highlights include 19 years at Intel where he was systems hardware designer, software designer, and strategic accounts manager. Mr. Gervasi subsequently was with S3 where he was a graphics architecture specialist and at Transmeta as memory technology analyst. Most recently he held several key positions with companies such as Netlist, SimpleTech, and US Modular driving unique memory module configurations. He is now Principal Systems Architect for Nantero, developing non-volatile RAM-class memories.

Mr. Gervasi has been involved in the definition of Double Data Rate SDRAM since its earliest inception. He has served on the JEDEC Board of Directors and chaired committees for DRAM parametrics and small form factor memory modules during the development of DDR1 through DDR5. He is currently the chairman of the JEDEC Non-Volatile Memory committee.

Page Updated January 12, 2024